Performance Evaluation of Different Topologies of SRAM and SRAM Memory Array Design at 180nm Technology

Memory circuits such as static random-access memory (SRAM) and dynamic (DRAM) form an integral part of system design contribute significantly to system-level power consumption. operating speeds dissipation have become important parameters due the explosive growth battery-operated appliances increased integration Hence SRAMs with different topologies are examined in terms like propagation delay, Static Noise Margin (SNM), corner analysis, by simulating using versatile tool cadence virtuoso at 180nm technology. Besides, topological performance comparison, SRAM array has also been illustrated from 2×2, 4×4 8×8, thereby verifying read write modes operation SRAM.